1. Field of the Invention
The invention relates to a method for forming an interlayer insulation film.
2. Description of Related Art
A technique in which a step part of a high aspect ratio is embedded and flattened by an interlayer insulation film formed at low temperature has increasingly been raised in importance along with enhancement of density and integration of LSI.
FIG. 3 is a process sectional view showing a conventional method for manufacturing a semiconductor device. Hereinafter, a method for manufacturing a conventional semiconductor device will be described by using FIG. 3.
First, a gate insulating film 53a and a polysilicon film 53b are deposited on a semiconductor substrate 51, and a gate pattern 53 is formed by patterning. Next, sidewalls 55 are formed on the side surfaces of the gate pattern 53, and a structure shown in FIG. 3(a) is obtained. At this time, step parts 56 are formed between the gate patterns 53.
Next, source/drain regions 57 are formed by performing impurity ion implantation in a self-aligning manner to the sidewalls 55. a silicon nitride film (SiN film) 59 used as a stopper film when contact openings are formed is formed thereon, obtaining a structure shown in FIG. 3(b).
Next, for instance, an interlayer insulation film 61 composed by a BPSG film is deposited at about 400 to about 500° C. by a SiH4—O2-base atmospheric pressure CVD method or a TEOS-O3-base CVD method, obtaining a structure shown in FIG. 3(c).
When the BPSG film 61 is deposited by the CVD method, the coverage of the BPSG film 61 is inferior in the step part 56 between the gates or the like, and the BPSG film 61 is formed in an overhanging shape. Thereby, voids 65 may be produced.
FIG. 4 is a plan view of the semiconductor substrate 51 on which elements are formed. Problems when voids 65 are produced will be described by using FIG. 4.
After the processes above, tungsten plugs 67 are usually formed arranged in parallel in the longitudinal direction of the gate pattern 53 in the step parts 56 between the gate patterns 53. Since the voids 65 are also formed in parallel in the longitudinal direction of the gate pattern 53, a problem occurs in that when the tungsten plugs 67 are formed by a CVD method or the like, tungsten enters into inside of the voids 65 and the adjacent tungsten plugs 67 are electrically connected.
The voids 65 are usually quenched by performing reflow of the BPSG film 61 by a heat treatment in a furnace of about 850° C. or lamp annealing of about 1000° C.
However, along with further miniaturization of a device, when the interlayer insulation film 61 is formed by embedding the above-mentioned BPSG film in a region between gates having a step part of a narrower pitch interval (for instance, the pitch being narrower than a gate space of 0.3 μm: the space being 0.2 μm or less after forming the sidewalls) and a high aspect ratio (for instance, an aspect ratio above 3), the coverage immediately after the film formation becomes worse, and voids 65 caused after the film formation become larger. A heat treatment in a furnace of at least 850° C. for about 15 minutes or a lamp annealing at 1000° C. for about 30 seconds is required as a reflow processing after the film formation so as to quench the voids 65. However, a demand for lowering a process temperature becomes more severe along with miniaturization of a device. When a heat treatment of 800° C. or higher is performed in a device of 0.18 μm or less, a problem occurs in that transistor characteristics such as suppression of short channel effect and driving current cannot be sufficiently secured. Therefore, a high temperature annealing condition cannot be used.
A method for forming a BPSG film by a twice divided process is disclosed as a conventional method for solving such a problem (for instance, refer to Japanese Unexamined Patent Publication No. 2001-345322). In this method, first, a first BPSG film is formed, and unevenness of the surface is then improved by applying a first heat treatment. Next, a second BPSG film is formed, and a second heat treatment is then applied.
However, when the BPSG film is formed by a twice divided process, an interface between an upper BPSG film and a lower BPSG film is exposed in a contact forming process or an interlayer CMP process which is a subsequent process, and an abnormal shape may be produced from an etch speed difference of a wet processing due to a difference between characteristics of the upper BPSG film and that of the lower BPSG film.
Also, a method for performing a reflow processing at low temperature by improving impurity concentration of the BPSG film is known.
When the impurity concentration of the BPSG film is improved, a temperature of a reflow processing can be lowered. However, since shrink fastening is insufficient, the film is not compact and becomes unstable.
Thus, it is difficult to form an excellent interlayer insulation film in which voids do not remain without damaging reliability of a device.